Field of the Invention
The present invention relates to a power semiconductor device and more particularly to a power semiconductor device including a semiconductor element and a wiring member connected with a solder.
Description of the Background Art
A general power semiconductor device has been conventionally manufactured in such a manner that, a lower surface electrode formed on a lower surface of a semiconductor element is bonded to a circuit pattern on an insulating substrate, and an upper surface electrode formed on an upper surface of the semiconductor element is electrically connected to another semiconductor element or an external terminal through an ultrasonic bonding wire made of aluminum. After that, sealing with a molding resin, or filling with a sealing member is performed.
However, in the case of the wire bonding, since an allowable current per wire is limited, the number of the wires needs to be increased in a power semiconductor device having a large-current circuit, which hampers productivity. Thus, according to a proposed method for wiring the large-current circuit to enhance the productivity, a plate-shaped wiring member formed by pressing a metal plate is bonded to the upper surface electrode of the semiconductor element with a solder (refer to Japanese Patent Application Laid-Open No. 2013-69825).
According to the power semiconductor device having the plate-shape wiring member described above, the plate-shape wiring member is arranged so as to cover the upper surface of the semiconductor element. Therefore, the problem is that a gap where the sealing member is unlikely to be filled is formed in a region not provided with the solder between the wiring member and the semiconductor element. In addition, in a case where the solder unnecessarily wets and spreads, the gap between the wiring member and the semiconductor element becomes narrower, so that the problem is that the sealing member is further unlikely to be filled.
Here, as for a case type power semiconductor device, unlike a mold type, it is difficult to apply a pressure with a die when the sealing member is filled, and penetration (filling) of the sealing member into the gap relies on natural penetrability, so that the sealing member is unlikely to be filled compared with the mold type. Especially, regarding to the above device, that is to say, a device in which the wiring member is integrated with the case, the wiring member is likely to be inclined depending on an assembled state of the case, and a distance between the semiconductor element and the wiring member is likely to vary. Therefore, the distance is likely to become small, which causes an oversupply of the solder and the solder is likely to wet and spread to an outside of a bonding region. As a result, the sealing member is more unlikely to be filled.
Here, in the case where the sealing member has not been filled in the gap for the above reason, in addition to causing an insulating property to be reduced as a matter of course, there is a reduction in mechanical strength of the sealing member for holding a bonding section between the wiring member and the semiconductor element. As a result, the semiconductor element and the solder bonding section cannot endure a thermal stress generated due to a change in temperature, and the problem is that the reliability is reduced.
Thus, in order to prevent the solder from wetting and spreading as described above, Japanese Patent Application Laid-Open No. 2013-69825 proposes a configuration in which a projection smaller than the upper surface electrode of the semiconductor element is provided in the wiring member. According to this configuration, since the oversupplied solder can be absorbed to a side of the projection as a fillet, the solder can stay in an inside of the upper surface electrode. However, the oversupplied solder still unnecessarily wets and spreads, and the sealing member is not sufficiently filled in some cases.